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HM62V256 Series
32,768-word x 8-bit Low Voltage Operation CMOS Static RAM
ADE-203-136E (Z) Rev. 5.0 Jun. 19, 1995 Features
* Low voltage operation SRAM Operating Supply Voltage: 2.7 V to 3.6 V * 0.8 m Hi-CMOS process * High speed Access time: 70/85/100 ns (max) * Low power Standby: 0.15 W (typ) * Completely static memory No clock or timing strobe required * Directly LVTTL compatible: All inputs and outputs
Ordering Information
Type No. HM62V256LFP-10T HM62V256LFP-7SLT HM62V256LFP-10SLT HM62V256LFP-8ULT HM62V256LT-10 HM62V256LT-8SL HM62V256LTM-10 HM62V256LTM-7SL HM62V256LTM-10SL HM62V256LTM-8UL Access Time 100 ns 70 ns 100 ns 85 ns 100 ns 85 ns 100 ns 70 ns 100 ns 85 ns 8 mm x 13.4 mm 28-pin TSOP (normal type) (TFP-28DA) 8 mm x 14 mm 32 pin TSOP (normal type) (TFP-32DA) Package 450 mil 280 pin plastic SOP (FP-28DA)
HM62V256 Series
Pin Arrangement
HM62W256LFP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top View) HM62W256LT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) HM62W256LTM Series
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2
22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top View)
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 V SS I/O2 I/O1 I/O0 A0 A1 A2
2
HM62V256 Series
Pin Description
Pin name A0 to A14 I/O0 to I/O7 CS WE OE NC VCC VSS Function Address inputs Data input/output Chip select Write enable Output enable No connection Power supply Ground
Block Diagram
V CC V SS
* * * * * * * *
(MSB) A12 A5 A7 A6 A8 A13 A14 A4 (LSB) A3 Memory Matrix 512 x 512
Row Decoder
* *
I/O0
* * * * *
* * * * * * *
Column I/O Column Decoder
* *
Input Data Control
* * *
I/O7
(LSB)
A2 A1 A0 A10 A9 A11
* *
(MSB)
* *
CS WE OE
Timing Pulse Generator Read/Write Control
3
HM62V256 Series
Function Table
WE X H H L L CS H L L L L OE X H L H L Mode Not selected Output disable Read Write Write VCC Current I SB , I SB1 I CC I CC I CC I CC I/O Pin High-Z High-Z Dout Din Din Ref. Cycle -- -- Read cycle (1)-(3) Write cycle (1) Write cycle (2)
Note: X: H or L
Absolute Maximum Ratings
Parameter Power supply voltage Terminal voltage
*1 *1
Symbol VCC VT PT Topr Tstg Tbias
Value -0.5 to 4.6 -0.5* to VCC+0.5 1.0 0 to + 70 -55 to +125 -10 to +85
2 *3
Unit V V W C C C
Power dissipation Operating temperature Storage temperature Storage temperature under bias
Notes: 1. Relative to VSS 2. VT min: -3.0 V for pulse half-width 50 ns 3. Maximum voltage is 4.6V
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input high(logic 1) voltage Input low(logic 0) voltage Note: VIH VIL Min 2.7 0 0.7V CC -0.3
*1
Typ 3.0 0 -- --
Max 3.6 0 VCC+0.3 0.2V CC
Unit V V V V
1. VT min: -3.0 V for pulse half-width 50 ns
4
HM62V256 Series
DC Characteristics (Ta = 0 to +70C, VCC = 2.7 V to 3.6V, VSS = 0 V)
Parameter Input leakage current Output leakage current Operating power supply current (DC) Symbol Min |ILI| |ILO | I CCDC1 I CCDC2 Average operating power supply current HM62V256-7 I CCAC1 -- -- -- -- -- Typ*1 -- -- -- -- -- Max 1 1 15 10 30 Unit A A mA mA mA Test conditions VSS Vin VCC CS = VIH or OE = VIH or WE = VIL, VSS VI/O VCC CS = VIL, others = VIH/VIL I I/O = 0 mA CS 0.2 V, V IH V CC - 0.2 V, VIL 0.2 V, II/O = 0 mA min cycle, duty = 100 %, I I/O = 0 mA CS = VIL, others = VIH/VIL
HM62V256-8
I CCAC1
-- -- --
-- -- --
27 24 15 mA Cycle time 1 s, duty = 100% I I/O = 0 mA, CS 0.2 V, VIH V CC - 0.2 V, VIL 0.2 V CS = VIH Vin 0 V, CS V CC - 0.2 V,
HM62V256-10 I CCAC1 I CCAC2
Standby power supply current
I SB I SB1
-- -- -- --
0.1 0.05 0.05 0.05 -- --
1 50 10 4*3 0.2 --
*2
mA A
Output low voltage Output high voltage
VOL VOH
-- VCC - 0.2
V V
I OL = 20 A I OH = -20 A
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. This characteristic is guaranteed only for L-SL version. 3. This characteristic is guaranteed only for L-UL version.
Capacitance (Ta = 25C, f = 1.0 MHz)
Parameter Input capacitance
*1 *1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 5 8
Unit pF pF
Test Conditions Vin = 0 V VI/O = 0 V
Input/output capacitance Note:
1. This parameter is sampled and not 100% tested.
5
HM62V256 Series
AC Characteristics (Ta = 0 to +70C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions * Input pulse levels: 0.4 V to 2.4 V * Input rise and fall time: 5 ns * Input and output timing reference level: 1.4 V
Output Load
Dout
500 50 pF* 1.4 V
(Including scope & jig)
Read Cycle
HM62V256 -7 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip selection to output in low-Z Output enable to output in low-Z Chip deselection to output in high-Z Output disable to output in high-Z Output hold from address change Symbol Min t RC t AA t ACS t OE t CLZ t OLZ t CHZ t OHZ t OH 70 -- -- -- 10 5 0 0 10 Max -- 70 70 35 -- -- 25 25 -- -8 Min 85 -- -- -- 10 5 0 0 10 Max -- 85 85 45 -- -- 30 30 -- -10 Min 100 -- -- -- 10 5 0 0 10 Max -- 100 100 50 -- -- 35 35 -- Unit ns ns ns ns ns ns ns ns ns 2 2 1, 2 1, 2 Notes
Notes: 1. t CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested.
6
HM62V256 Series
Read Timing Waveform (1) (WE = VIH)
t RC
Address
Valid address t AA t ACS
CS t OH t OE t OLZ OE t OHZ t CHZ Dout High impedance Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL )
t RC Address tAA t OH Dout Valid data Valid address t OH
Read Timing Waveform (3) (WE = VIH, OE = VIL )*1
t ACS CS t CLZ High impedance
t CHZ Valid data
Dout
Note: 1. Address must be valid prior to or simultaneously with CS going low.
7
HM62V256 Series
Write Cycle
HM62V256 -7 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Symbol Min t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ 70 50 0 50 45 0 0 30 0 10 0 Max -- -- -- -- -- -- 25 -- -- -- 25 -8 Min 85 75 0 75 55 0 0 35 0 10 0 Max -- -- -- -- -- -- 30 -- -- -- 30 -10 Min 100 80 0 80 60 0 0 40 0 10 0 Max -- -- -- -- -- -- 35 -- -- -- 35 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 7 3, 8 6 1, 2, 7 4 5 Notes
Notes: 1. t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. t CW is measured from CS going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention, tWP tWHZ max + tDW min.
8
HM62V256 Series
Write Timing Waveform (1) (OE Clock)
t WC Address
Valid address t AW t WR
OE t CW CS
*1
t AS
t WP
WE t OHZ Dout High impedance t DW Din High impedance t DH
Valid data
Notes: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state.
9
HM62V256 Series
Write Timing Waveform (2) (OE Low Fixed)
t WC Address
Valid address t CW t WR
CS
*1
t AW tWP WE tAS t WHZ Dout t DW Din High impedance t DH
*4
t OH
t OW
*2
*3
Valid data
Notes: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 2. Dout is the same phase of the write data of this write cycle. 3. Dout is the read data of next address. 4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the output must not be applied to them.
10
HM62V256 Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
Parameter VCC for data retention Data retention current Symbol VDR I CCDR Min 2.0 -- -- -- Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. 5. 6. t CDR tR 0 t RC
*5
Typ*1 Max -- 0.05 0.05 0.05 -- -- 3.6 27 7*3 2*4 -- --
*2
Unit V A
Test conditions*6 CS V CC - 0.2 V, Vin 0 V VCC = 2.7 V, Vin 0 V CS V CC - 0.2 V
ns ns
See retention waveform
Typical values are at VCC = 2.7 V, Ta = 25C and not guaranteed. 9 A max at Ta = 0 to 40C. This characteristics guaranteed for only L-SL version. 2.0 A max at Ta = 0 to 40C. This characteristics guaranteed for only L-UL version. 0.4 A max at Ta = 0 to 40C. t RC = read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low VCC Data Retention Timing Waveform
Data retention mode V CC 2.7 V t CDR 0.7 V CC V DR CS 0V CS > VCC - 0.2 V tR
11
HM62V256 Series
Package Dimensions
HM62V256LFP Series (FP-28DA)
18.00 18.75 Max 28 15 8.40
Unit: mm
1 1.27 Max
14
3.00 Max
+ 0.08 - 0.07
11.80 0.30 1.70 0 - 10
1.27 0.10
0.40 - 0.05
0.20 0.10
+ 0.10
0.17
1.00 0.20
HM62V256LT Series (TFP-32DA)
8.00 8.20 Max 32 17
Unit: mm
1
16 0.50
0.20 0.10
0.08 M 14.00 0.20 0.80 0-5 0.50 0.10
0.45 Max 0.17 0.05 1.20 Max
12.40
0.10
12
0.13 0.05
HM62V256 Series
HM62V256LTM Series (TFP-28DA)
8.00 8.15 Max 21 8 Unit: mm
22 0.20
+0.10 -0.05
7 0.55 0.10 M 0.63 Max 13.4 0.3 5 Max 0.50 0.10 0.80
1.2 Max
11.80
0.10
0.15
0.05 -0.05
+0.05 -0.02
+0.10
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